SMIC Adopts Cadence Digital Flow with Advanced Features for Improving Area, Power and Performance

SAN JOSE, Calif., Sept. 4, 2013 /PRNewswire/ --

Highlights:

• SMIC's new 40nm Reference Flow 5.1 incorporates the state-of-the-art Cadence CCOpt and GigaOpt technology and the Tempus Timing Signoff Solution
• The new RTL-to-GDSII digital flow supports the Cadence hierarchical low-power flow and the latest version of the Common Power Format (CPF)

Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, and Semiconductor Manufacturing International Corporation ("SMIC;" NYSE: SMI; SEHK: 981), mainland China's largest and most advanced semiconductor foundry, today jointly announced that SMIC has adopted the Cadence® digital tool flow-for the new SMIC Reference Flow 5.1, a complete RTL-GDSII digital flow for low-power designs. The Cadence flow incorporates advanced features to help mutual customers improve power, performance and area for 40nm chip design. Cadence tools used in the flow are RTL Compiler, Encounter® Digital Implementation System, Encounter Conformal® Low Power, Cadence QRC Extraction, Tempus^TM Timing Signoff Solution, Encounter Power System, Physical Verification System, and Cadence CMP Predictor.

SMIC's new Reference Flow 5.1 supports Cadence Clock Concurrent Optimization (CCOpt) technology, a key feature of the Cadence Encounter Digital Implementation System. The qualification process demonstrated that, compared to traditional clock tree synthesis, CCOpt can improve power by 14 percent, area by 11 percent and performance by 4 percent on SMIC's 40nm process.

Other advances include support for:

• The Cadence hierarchical low-power digital flow, which incorporates CPF 2.0, the latest version of the popular power format.
• The Cadence Physical Verification System (PVS) by including SMIC's first online 40nm DRC/LVS deck for Cadence PVS as well as SMIC's first 40nm PVS dummy insertion rule deck.
• GigaOpt technology, which delivers RTL-to-GDSII core optimization.

"We have worked closely with Cadence to ensure our mutual customers can confidently move forward using the latest Cadence digital tools to manufacture silicon at SMIC's 40-nanometer process," said Tianshen Tang, Senior Vice President of SMIC Design Service. "This new reference flow offers our customers advanced technologies that can improve key metrics such as power, performance and area."

"SMIC's Reference Flow 5.1 offers our customers a clear road map for moving efficiently from design to manufacturing while maximizing the quality of the silicon," said Dr. Chi-Ping Hsu, chief strategy officer and senior vice president of digital and signoff group at Cadence. "As the complexities inherent in chip design continue to grow, Cadence will continue working closely with SMIC to offer our customers the powerful automation tools they need to succeed."